Field
The present disclosure relates generally to pulse generator circuitry, and more particularly, to pulse generator circuitry that may have better scaling across process, voltage, and temperature.
Background
In some examples, a pulse latch is an active-high latch clocked by a narrow pulse. The narrow pulse may be generated from the rising edge of a clock. A pulse-latch may provide substantial performance and clock power benefit compared to regular flip-flops. However, pulse-latches may be difficult to design. Additionally, pulse-latches may have a poor yield in some process technologies. One aspect of pulse latch designs is the control of the pulse-width used to clock the pulse latch. The pulse-width may impact the ability of the pulse latches to be written, which may be referred to as “write-ability.”
In current pulse generator (“pulser”) designs, pulse width and functional latch write path delay do not scale in the same way across process, voltage, and temperature (PVT). Because pulse width and functional latch write path delay do not scale in the same way in current pulse generator designs across PVT, extra buffers in the pulse generator delay path may be added to ensure that latches are able to be written for all cases. The extra buffers result in higher hold-time, clock power, and area for the circuitry, however.